1. Field of the Invention
The present invention relates to a package manufacturing method and semiconductor device.
2. Description of the Related Art
In recent image sensors such as a CCD image sensor and CMOS image sensor, digitization of output electrical signals increases the number of output electrical signals. This boosts the need to increase the number of output terminals of the package. Further, image sensors and products containing the packages of the image sensors are shrinking in size. The package needs to increase the packaging density that is the number of output terminals per unit packaging area of the package. However, decreasing the pitch between output terminals of the package has a limit, so the packaging density needs to be increased without decreasing the pitch. As a package that satisfies these demands, there is proposed a land grid array (LGA) package in which land electrodes are two-dimensionally arrayed on the bottom surface of the package.
Japanese Patent Laid-Open No. 2002-246532 discloses a method of manufacturing a land grid array (LGA) semiconductor device in which a semiconductor device is held on a surface opposite to the bottom surface of a wiring board having a plurality of land electrodes on the bottom surface, and is electrically connected to the electrodes. More specifically, as shown in FIG. 3(a) of Japanese Patent Laid-Open No. 2002-246532, a metal plate is stamped or etched, integrally molding a lead frame 10 having a die pad 13, inside inner leads 14A, and outside inner leads 14B. Recesses 14b, and projections 14a serving as lands are formed on the bottom surface of the lead frame 10. As shown in FIG. 3(b) of Japanese Patent Laid-Open No. 2002-246532, an adhesive tape 20 is adhered to the bottom surfaces of the die pad 13, inside inner lead 14A, and outside inner lead 14B. Then, as shown in FIG. 3(c) of Japanese Patent Laid-Open No. 2002-246532, a cutting punch 21 is used to punch the region between the die pad 13 and the inside inner lead 14A or that between the inside inner lead 14A and the outside inner lead 14B. As a result, the die pad 13 and the inside inner lead 14A are isolated as shown in FIG. 3(d) of Japanese Patent Laid-Open No. 2002-246532. A semiconductor device is fixed to the die pad 13, the external terminals of the semiconductor device are connected to the inside inner leads 14A and outside inner leads 14B, and the adhesive tape 20 are removed. After that, as shown in FIG. 5(b) of Japanese Patent Laid-Open No. 2002-246532, the semiconductor device and lead frame 10 are sealed with a resin. According to Japanese Patent Laid-Open No. 2002-246532, a compact lead frame having a land grid array can be easily formed from a single-layered metal plate.
Japanese Patent Laid-Open No. 2001-24083 discloses a method of manufacturing a resin-sealed semiconductor device in which a plurality of land electrodes electrically connected to a semiconductor device are arrayed on the bottom surface. More specifically, as shown in FIG. 4 of Japanese Patent Laid-Open No. 2001-24083, a punching member 17 punches a metal plate 13 so as to cut it halfway, thereby forming a terminal land frame including land structures 12 as shown in FIG. 2 of Japanese Patent Laid-Open No. 2001-24083. As shown in FIG. 9(b) of Japanese Patent Laid-Open No. 2001-24083, a semiconductor device 30 is bonded to a surface of the terminal land frame on which land structures 28 project. As shown in FIG. 9(c) of Japanese Patent Laid-Open No. 2001-24083, the semiconductor device 30 is wire-bonded to a land structure 28c and the like. As shown in FIG. 9(d) of Japanese Patent Laid-Open No. 2001-24083, the terminal land frame and semiconductor device 30 are sealed with a sealing resin 32. Then, as shown in FIG. 9(e) of Japanese Patent Laid-Open No. 2001-24083, the bottom surfaces of the land structures 28 are pushed up by a push pin from below them, thereby applying a press force. Accordingly, the land structures 28 are separated from a frame main body 26, as shown in FIG. 9(f) of Japanese Patent Laid-Open No. 2001-24083. In Japanese Patent Laid-Open No. 2001-24083, the land structures 28 are buried in the sealing resin 32 and formed inside it without peeling off. A resin-sealed semiconductor device having land electrodes can therefore be implemented.
In the manufacturing method described in Japanese Patent Laid-Open No. 2001-24083, the land structures 28 are separated from the frame main body 26 by directly applying a press force to prospective land electrode surfaces (bottom surfaces of the land structures 28).
The manufacturing method described in Japanese Patent Laid-Open No. 2002-246532 does not mention how to hold the isolated inside inner leads 14A when sealing the semiconductor device and lead frame 10 with a resin. If the isolated inside inner leads 14A are not held when sealing the semiconductor device and lead frame 10 with a resin, they may be misaligned. The misaligned inside inner leads 14A may be short-circuited to the die pad 13 or outside inner leads 14B, decreasing the efficiency percentage, that is, yield in the package manufacturing process.